The present invention relates to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) type read only memory (ROM) and a method of manufacturing the same.
Data is written in a read only memory (ROM) during its manufacturing process. A ROM of this type is called a mask programmable ROM. Data writing is performed by (1) a contact method, (2) a field oxide method, or (3) a threshold voltage method. In the contact method, an output line is connected to or disconnected from the drain of a memory cell transistor to write data of logic "1" or "0". In the field oxide method, a gate oxide film is formed in a gate region of the memory transistor to write data of logic "1" or a field oxide film is formed to write data of logic "0". Finally, in the threshold voltage method, a threshold voltage is either increased or not increased to write data of logic "1" or "0".
According to the contact method, one contact is required for each memory cell. On the other hand, according to the field oxide and threshold voltage methods, only one contact is required for every two memory cells. In this sense, a memory size based upon the field oxide and the threshold voltage methods is smaller than that based upon the contact method.
FIG. 1 is a circuit diagram of a MOS type ROM, and FIG. 2 is a plan view showing part (i.e., a contact portion and its periphery) of the circuit of FIG. 1 which is prepared in accordance with the field oxide method. Reference numerals: 1 denotes gate wiring layers of memory cells 6; 2, ROM output lines; 3, ground lines; 4, MOS transistors each constituting the memory cell 6; and 5, contacts each connecting a given output line 2 and a corresponding memory cell 6. The gate wiring layer 1 comprises polysilicon, and the output line comprises aluminum.
As is apparent from the above in the field oxide method, only one contact 5 is required for every two memory cells 6. In contrast to the contact method, the field oxide method can decrease the memory size. The length of a memory cell is determined by the size of the contact 5 and a distance l between the gate wiring layer and the contact 5. When the contact 5 is decreased to a given size, the resistance of the contact portion is increased to a degree that cannot be disregarded. For this reason, reduction of the contact size is limited, thereby restricting decrease in the memory size.